1. Field of the Invention
The present invention relates to a reference voltage generating circuit generating reference voltage (comparison voltage) to be supplied to a comparator and more specifically, relates to a technique effectively used in a reference voltage generating circuit less susceptible to fluctuations in supply voltage and temperature, and a receiver circuit including the reference voltage generating circuit.
2. Description of the Related Art
One of the standards for communication between home electric appliances is the home bus system (HBS). In some HBS systems, transmission paths are composed of twisted pair lines, and digital signals are transmitted through the transmission paths using AMI (alternate mark inversion) coded signals (hereinafter, referred to as AMI signals). The AMI signals take three values: zero, positive, and negative values. In a communication using the AMI signals, data is transmitted with logical “0” indicated by zero and logical “1” indicated by alternating the polarity. The transmitted waveform is therefore close to that of an alternating-current signal. Accordingly, the transmission is resistant to noise, and the HBS implements stable data transmission. The polarity of the logical “1” is positive or negative with respect to the electrical potential of the logical “0”. The electrical potential of the logical “0” is not limited to 0V and can be 5V or the like, for example.
As the devices which are mounted on the appliances constituting a system to which the HBS is applied and have a function to communicate among the appliances, HBS driver/receiver ICs (semiconductor integrated circuits) have been provided. Such an HBS driver/receiver IC includes a transmission drive circuit configured to generate and send AMI signals to a transmission path. The HBS driver/receiver IC further includes therein a receiver circuit configured to judge the logic level of the AMI signals on the transmission path and regenerate received data. The receiver circuit includes a comparator configured to compare the received signals with a predetermined reference voltage (comparison voltage) for judging the logic level thereof, and a reference voltage generating circuit configured to generate the reference voltage.
The reference voltage generating circuit includes: a constant current circuit configured to output constant current; a bias circuit (constant voltage (reference voltage) circuit) configured to generate bias voltage for the constant current circuit; a current-to-voltage converting circuit configured to convert current generated by the constant current circuit to voltage as the reference voltage; and the like. Such a reference voltage generating circuit is described in Japanese Patent Laid-open Publication No. 2003-207527, for example. Moreover, one of the inventions concerning the receiver circuits in the systems to which the HBS is applied is described in Japanese Patent Laid-open Publication No. 2007-318632, for example.
In the systems to which the HBS is applied, the transmission path may be very long and is, for example, equal to or more than several tens meters in some cases. In such a system, the long transmission path can cause distortion in the waveform of the transmission signal or reduce the amplitude of the signal. In the case where an appliance connected through the HBS includes a load which requires a large amount of power and repeatedly starts and stops like an air conditioner including a compressor, electric current rapidly changes at the start and stop of the load. This can cause fluctuations in the supply voltage. In the receiver circuit, the reference voltage accordingly changes, thus may cause errors in the judgment of the received data.
When the communication between such appliances employs the HBS, therefore, the reference voltage generating circuit used in the receiver circuit is required to generate stable reference voltage even if the supply voltage fluctuates. The inventors conceived a circuit shown in FIG. 5 as the reference voltage generating circuit to be used in the receiver circuit.
The circuit shown in FIG. 5 includes a differential amplifying section 11, a received data judging section 12, and a reference voltage generating section 13. The differential amplifying section 11 receives AMI-coded differential input signals from a transmission path and amplifies the same. The received data judging section 12 compares the signals amplified by the differential amplifying section 11 with reference voltage Vref for judging the received data. The reference voltage generating section 13 generates the reference voltage Vref. The reference voltage generating section 13 includes a constant current circuit having an insulated gate field effect transistors (hereinafter, referred to as MOS transistors) M0 to M3 and resistors R1 and R3. The MOS transistor M0 and resistor R1 are connected in series between a supply voltage terminal VDD and a ground potential point GND. The gate of the MOS transistor M1 is connected to a node N1 connecting the resistor R1 with the MOS transistor M0, and the resistor R3 is connected between the source of the MOS transistor M1 and the ground potential point GND. The MOS transistor M2 is connected to the drain of the MOS transistor M1 and the supply voltage terminal VDD. The MOS transistor M3 forms a current mirror in conjunction with the MOS transistor M2. The gate of the MOS transistor M0 is connected to a node N2 connecting the MOS transistor M1 with the resistor R3. Current I1 of the MOS transistor M2 is thus transferred to the MOS transistor M3 so that constant current I2 flows from the MOS transistor M3.
The constant current I2 flowing from the constant current circuit is transferred by a current mirror circuit composed of MOS transistors M4 and M5 to flow through a resistor R7 for current-to-voltage conversion. The reference voltage Vref based on the supply voltage VDD is thus generated.
In the reference voltage generating circuit as shown in FIG. 5, the current I1 of the MOS transistor M1 of the constant current circuit is determined by the resistance value of the resistor R3 and the potential V2 of the node N2 as I1=V2/R3. Here, the potential V2 of the node N2 is fixed to a potential higher than the ground potential GND by a threshold voltage Vth of the MOS transistor M0. That is to say, the potential V2 is substantially constant, thereby the current I1 flowing through the resistor R3 and MOS transistors M1 and M2 may be made to be constant. Moreover, since the potential V2 is determined based on the ground potential GND, the potential V2 remains substantially constant even if the supply voltage fluctuates. Accordingly, there is little change in the current I1. The current I2, which is proportional to the current I1, and the current I3 flowing through the resistor R7 therefore will not fluctuate. The relative potential of the reference voltage Vref (=I3·R7) to the supply voltage changes little even if the supply voltage fluctuates. The reference voltage generating circuit shown in FIG. 5 thus has an advantage of less dependency on the supply voltage.
In the circuit shown in FIG. 5, however, the potential V2 of the node N2 is determined by the threshold voltage Vth of the MOS transistor M0. The MOS transistor M0 does not have much influence on the potential V2 of the node N2 because the threshold voltage Vth of the MOS transistor M0 has a small temperature coefficient. However, the resistance value of the resistor R3, which is connected to the MOS transistor M1 in series, changes as the ambient temperature changes because of the temperature characteristic of the resistor R3. The current I1 therefore changes comparatively greatly as temperature changes as indicated by a dashed line B1 in FIG. 4A, thus leading to fluctuations in the reference voltage Vref.
In short, in the circuit shown in FIG. 5, the reference voltage Vref changes depending on the ambient temperature. The changes in the reference voltage Vref result in degradation of the receiving sensitivity of the receiver circuit, and the level of the received signal cannot be correctly judged. It is therefore revealed that the circuit shown in FIG. 5 has a problem that more errors will occur in the received data. Herein, the signals supplied from the differential amplifying section 11 to the received data judging section 12 are indicated by Vi1 and Vi2. When Vi1<Vref and Vi2<Vref, the receiving sensitivity is defined by a potential difference between Vi1 and Vi2. The smaller the fluctuations in this potential difference, the better the receiving sensitivity.